1. Field of the Invention
The present invention generally relates to a power-saving apparatus and a method thereof for sharing electric charges, and more particularly, to an analog power-saving apparatus and a method thereof for sharing electric charges.
2. Description of Related Art
In general, an analog circuit employs an operational amplifier (OPA) to drive a load capacitor to provide a required output voltage available for an application circuit. FIG. 1 is a conventional circuit diagram showing an OPA 101 is used to drive a load capacitor CL, wherein the positive input terminal (+) of the OPA 101 is for receiving an analog voltage VDAC generated by a digital code DS received by a digital-to-analog converter (DAC) 103, and the output terminal of the OPA 101 connects the negative input terminal (−) thereof to together form a unit gain amplifier so as to drive the load capacitor CL and thereby provide an output voltage VOUT available for a needed application device.
FIG. 2 is a signal waveform diagram of the analog voltage VDAC and the output voltage VOUT in FIG. 1. Referring to FIGS. 1 and 2, it can be seen from FIG. 2 in a duration T1 where the analog voltage VDAC steeply rises from a low voltage level to a high voltage level, the OPA 101 charges the load capacitor CL, and the duration T1 would cause a power consumption of the above-mentioned application device. On the other hand, in a duration T2 where the analog voltage VDAC steeply falls from the high voltage level to the low voltage level, the electric charges stored in the load capacitor CL would be discharged through the OPA 101, so that the output voltage VOUT also falls from the high voltage level to the low voltage level, and, thus, the duration T2 does not cause any power consumption of the above-mentioned application device.
Based on the above description, some analog circuit designers proposed a power-saving method for sharing electric charges that recycling the above-mentioned released electric charges, then distributing the recycled released electric charges to the load capacitor CL during the output voltage VOUT rises again from the low voltage level to the high voltage level, further using the OPA 101 to drive the load capacitor CL with released electric charges from distributing, so as to establish a power-saving mechanism for the application device.
FIG. 3 is a circuit diagram of a conventional power-saving apparatus 300 commonly used for sharing electric charges and FIG. 4 is a signal waveform diagram of the analog voltage VDAC and the output voltage VOUT of the power-saving apparatus 300 for sharing electric charges in FIG. 3 including the control signals CS1 and CS2 of two switches SW1 and SW2 thereof. Referring to FIGS. 3 and 4, the digital system of the above-mentioned application device usually is informed of the status of the digital code DS received by the DAC 103 during each of durations TP1-TP3.
First in the duration TP1, the digital system of the above-mentioned application device is informed of that the status of the digital code DS received by the DAC 103 in the entire duration TP1 is the analog voltage VDAC in the high voltage level; thus, the digital system of the above-mentioned application device would send out the control signals CS1 and CS2 in the duration T1 so as to turn off the switch SW1 and turn on the switch SW2. At the time, the electric charges in a storing/sharing capacitor CEQ stored prior to the duration T1 would be distributed to the load capacitor CL. It can be seen before an OPA 201 is used to drive the load capacitor CL, the voltage across both terminals of the load capacitor CL has the voltage level of the sharing voltage VEQ of the storing/sharing capacitor CEQ already.
Next, the digital system of the above-mentioned application device would send out the control signals CS1 and CS2 again in a duration T2 so as to turn on the switch SW1 and turn off the switch SW2. Since the voltage across both terminals of the load capacitor CL at the time is the voltage level of the sharing voltage VEQ of the storing/sharing capacitor CEQ already, the OPA 201 drives the load capacitor CL merely from the level of the sharing voltage VEQ up to the analog voltage VDAC in the high voltage level. After that, the digital system of the above-mentioned application device would once again send out the control signals CS1 and CS2 in a duration T3 so as to turn off the switch SW1 and turn on the switch SW2, and in this way, the electric charges in the load capacitor CL to be released are stored in the storing/sharing capacitor CEQ.
Then in the duration TP2, the digital system of the above-mentioned application device is informed of that the status of the digital code DS received by the DAC 103 in the entire duration TP2 is the analog voltage VDAC in the low voltage level; thus, the storing/sharing capacitor CEQ in a duration T4 need not distribute electric charges to the load capacitor CL. In the duration T4, the digital system of the above-mentioned application device sends out the control signals CS1 and CS2 to turn off the switches SW1 and SW2.
After that, the digital system of the above-mentioned application device would send out the control signals CS1 and CS2 in a duration T5 to turn on the switch SW1 and turn off the switch SW2, so that the OPA 201 pulls the level of the output voltage VOUT to the analog voltage VDAC in the low voltage level. Finally in a duration T6, the load capacitor CL need not release electric charges to the storing/sharing capacitor CEQ, so that the digital system of the above-mentioned application device sends out the control signals CS1 and CS2 again to turn off the switches SW1 and SW2 in the duration T6.
Further in the duration TP3, the digital system of the above-mentioned application device is informed of the status of the digital code DS received by the DAC 103 in the entire duration TP3 is the analog voltage VDAC in the high voltage level. Thus, the digital system of the above-mentioned application device would send out the control signals CS1 and CS2 to turn off the switch SW1 and turn on the switch SW2 in a duration T7. At this time, the electric charges in the storing/sharing capacitor CEQ stored prior the duration T3 would be distributed to the load capacitor CL. It can be seen before an OPA 201 is used to drive the load capacitor CL, the voltage across both terminals of the load capacitor CL already has the voltage level of the sharing voltage VEQ of the storing/sharing capacitor CEQ.
Furthermore, the digital system of the above-mentioned application device sends out the control signals CS1 and CS2 again to turn on the switch SW1 and turn off the switch SW2 in a duration T8. Since the voltage across both terminals of the load capacitor CL at this time is the voltage level of the sharing voltage VEQ of the storing/sharing capacitor CEQ, the OPA 201 drives the load capacitor CL merely from the level of the sharing voltage VEQ UP to the analog voltage VDAC in the high voltage level. In the end, the digital system of the above-mentioned application device would once again send out the control signals CS1 and CS2 in a duration T9 so as to turn off the switch SW1 and turn on the switch SW2, and in this way, the electric charges in the load capacitor CL to be released are stored in the storing/sharing capacitor CEQ in advance. By cyclically performing the above-described operation flowchart, the power-saving goal of the above-mentioned application device is achieved.
However, the above-described mechanism using the digital system of the above-mentioned application device is defective in deciding when the electric charges of the storing/sharing capacitor CEQ need to be shared with the load capacitor CL and deciding when the electric charges in the load capacitor CL to be released need to be stored in the storing/sharing capacitor CEQ.
For example, first, assuming in the above-mentioned duration TP2, the status of the digital code DS received by the DAC 103 is the analog voltage VDAC in the high voltage level, thus, the digital system of the above-mentioned application device is informed of the status of the digital code DS received by the DAC 103 in the entire duration TP2 is the analog voltage VDAC in the high voltage level. In the duration T4, the electric charges in a storing/sharing capacitor CEQ stored prior to the duration T3 would be distributed to the load capacitor CL. Thus, the digital system of the above-mentioned application device would send out the control signals CS1 and CS2 to turn off the switch SW1 and turn on the switch SW2.
Further in the durations T2-T4, the output voltage VOUT must fall from the high voltage level to the level of the sharing voltage VEQ first, followed by rising to the high voltage level in the duration T5, but such a course still causes power consumption of the above-mentioned application device. In addition, in the duration when the electric charges stored in the storing/sharing capacitor CEQ must be distributed to the load capacitor CL and the electric charges stored in the storing/sharing capacitor CEQ is less than the electric charges stored in the load capacitor CL, although the electric charges stored in the storing/sharing capacitor CEQ are supposedly to be distributed to the load capacitor CL, but the real course is the opposite to the above mentioned that the load capacitor CL would share the electric charges stored therein with the storing/sharing capacitor CEQ, which causes more power consumption of the above-mentioned application device.